On 12/09/2011 10:17 AM, gianni borghesan wrote:
> Hi Nick...
> I was looking at your code, and i have a doubt:
> when your are in the running state of the application fsm, you do not
> have transitions at each iteration step. i would expect that a
> coordination between HW and the itasc block, like:
>
> read data
> compute...
> write
>
> is this in other places? or it should be placed there (unless of course
> you just run periodically your HW interfaces, but then if the Ts are
> comparable you might have some delay...)
The examples have indeed HW interfaces running periodically.
The design allows you to coordinate between application level (HW) and itasc level,
by putting a coordination fsm in the running state of the application level, in the same way this is done between the itasc and task level.
In this case, you'll have to disconnect the timer from the itasc level and make sure to send trigger events (raise_trigger_event) in the application fsm, if the event is
meant to be for the itasc level
(is standard like this, but good to check it :) )

nick
> Gianni.