On Thu, 12 May 2011, gianni borghesan wrote:

> Hi all,
>
> I was wondering which strategy i should adopt to have a set of
> computation, in different components done in the same time step.
> The idea is:
> let say that you want to make a 1-1 translation (blocks->components) of
> a simulink scheme (of course with only discrete time system).
> as many of you probably knows, simulink differentiate between blocks
> that use the input to compute the output, and blocks that don't
> (strictly proper systems).
> If you have a cascade of blocks, say pluses and multiplies, all sinking
> in a delay or memory block (any strictly proper system), you know that
> at each time step, the input of the last block is the full set of
> operations.
> I.E. the engine of simulink is aware which operations should be done in
> an "atomic way" and which not.

No: it _imposes_ such a Coordination upon its users, without allowing them
to Configure it, except by means of such a "dirty hack" that fundamentally
changes the dynamical model of your controller... Sigh. (But most Simulink
users don't seem to care about this abuse. Just as they don't seem to care
about the lock-in by Skype-now -Microsoft or other such proprietary
protocol imposers. But that's another story :-))

> If I do the same in orocos with ports without any particular control, I
> assume, you do not get the same results.

Of course not: we allow (or rather, "force" :-) you to decide on our
computational scheduling policy yourself. In other words, _you_ must decide
how you are going to solve the 'algebraic loop'.

> how to do that (providing that you want to implement a non strictly
> proper system as a cascade of non strictly proper components)?

Since most controllers are not distributed anyway, putting them in
"Components" is a very heavyweight solution, to start with. It's much more
efficient to make one Component, whose activity consists of calling the
_functiona_ of each block in an appropriate order. This order could be
encoded as a DAG (Direct Acyclic Graph), which represents _your_choice of
computational causality. These computations share the "state" of the system
as common variables, accessible to all computations. THis state will be
Configured in the configure_hook of your Component.

We are currently designing such datastructures; the tooling to
automatically convert a Component-based version of the system into the
above-mentioned DAG-scheduled computation will require more work.

I would be very happy if someone could dedicate a couple of manweeks to
this effert... It will go together with the "executable graph" design and
implementation that is also going on in Leuven.

Summary: design your control architecture with Components and Ports,
because (i) that is the most reusable design, since it can be
distributed when needed, and (ii) the "programming to Ports" approach
naturally leads to a "no side-effects" style of programming, which is also
most reusable.

The good news: this suggestion can make your code lightning fast without
giving in on reusability
The bad news: the required generic infrastructure that is behind all
possible controllers does not yet exist.

> Thanks in advance, Gianni.

Herman

2011/5/12 gianni borghesan <Gianni [dot] Borghesan [..] ...>

> Hi all,
>
> I was wondering which strategy i should adopt to have a set of
> computation, in different components done in the same time step.
> The idea is:
> let say that you want to make a 1-1 translation (blocks->components) of
> a simulink scheme (of course with only discrete time system).
> as many of you probably knows, simulink differentiate between blocks
> that use the input to compute the output, and blocks that don't
> (strictly proper systems).
> If you have a cascade of blocks, say pluses and multiplies, all sinking
> in a delay or memory block (any strictly proper system), you know that
> at each time step, the input of the last block is the full set of
> operations.
> I.E. the engine of simulink is aware which operations should be done in
> an "atomic way" and which not.
>
> If I do the same in orocos with ports without any particular control, I
> assume, you do not get the same results.
>
> how to do that (providing that you want to implement a non strictly
> proper system as a cascade of non strictly proper components)?
>
> Thanks in advance, Gianni.
>
>
I usually use either Master/Slave activities (you have one monitoring
component that awakes all component of the loop each period) or a clocking
component publishing an eventPort "outClock" that I connect to the "inClock"
eventPort of the first loop component which awakes the following component
with a outCLock port.

I don't really know if these are good ways to do it (and which is the better
between the both).

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